CMOS technology has been long neglected owing to high production cost, which only lately have been reduced thanks to improvements both in fabricating processes and in circuit schemes.
In the field of implementation of VLSI integrated circuit, CMOS technology presents a number of advantages.
When compared to implementations of equivalent complexity in NMOS technology, CMOS circuits are characterized by a very low dissipation limited only at switching instants, while under static conditions their dissipation is practically nill.
The instrinsically good noise-immunity makes CMOS cicuits suitable for use on board satellites and in telecommunication circuits in general, where reliability and noise immunity problems are more stringent.
They are also suitable for use in analog circuits: that allows the development of circuit systems comprising both analog and digital elements on the same chip.
In MOS-technology circuits generally in use, the timing control of the sequential-logic elements is effected by means of so called "transfer-gate" transistors, which interrupt or allow the signal flow on the line in a mode similar to the switching on/off of a switch. Such transistors are driven by two clock signals forming a two-phase timing. The two clock signals can simply have two opposite logic levels or provide also additional periods in which both present a non-active logic level, to assure greater stability in the signal logic levels.
The latter are referred to as "non overlapping phases" which, for implementation, need rather complex circuit structures which occupy significant portions of the integrated circuit area, and require great care to balance the load distributions on each of them so as not to alter phase relations of the produced signals.
In any case a two-phase timing requires the presence of two conduction paths inside the integrated circuit, with a consequent increase in circuit complexity.
A sequential logic basic-element in CMOS technology using a single clock signal is known and described in the article: "Efficient custom digital IC design for control applications" Proceedings of the 4th International Conference on Custom and Semi-custom ICs; 6-8 November 1984, London.
This known structure uses two PMOS and two NMOS transfer-gate transistors as well as a conventional CMOS inverter, the latter consisting of two enhancement MOS transistors, the one P-channel the other N-channel, arranged in series.
Even though this structure is implemented in CMOS technology, its operation is of "quasi-NMOS" type, i.e. the circuit is dissipative even under static conditions.
In addition the following critical condition occurs: when the input data and the clock signal, respectively applied to the channel and to the gate of the first NMOS transfer-gate transistor, are at logic level "1", the transistor transfers inside the structure a logic level affected by a considerable voltage drop due to the transistor threshold voltage and to "body effect" so as to make the datum assume an uncertain logic condition.